The development of microprocessors, following Moore's Law, has resulted in increasing on-chip power density, leading to thermal management challenges. CMOS processes have at least two components of power dissipation: 1) switching power, which is proportional to the square of the supply voltage and to clock frequency; and 2) device leakage power, which is a function of supply voltage.
Increasingly, micro-management of microprocessor supply voltage and clock frequency vis-à-vis its workload profile is used to gain significant power savings. Given that the main power dissipation mechanisms are strong functions of the supply voltage, significant power consumption reduction can be achieved with moderate reduction in the average supply voltage over time and usually with modest or no reduction in circuit performance.
Dynamic Voltage and Frequency Scaling (DVFS) techniques are used today at relatively low rates compared to the microprocessor rate of activity. The DVFS rate is currently limited by the voltage slew rate of available voltage regulators. The more closely the voltage regulator can track the microprocessor workload in real time, the more the time averaged supply voltage can be reduced, potentially resulting in significant power savings. Therefore, the full potential of existing DVFS techniques has been limited by voltage regulator technology.
For instance, some systems adjust the supply voltage and clock frequency at the Unix Kernel level with frequency being adjusted about every 10 us. Supply voltage is adjusted less frequently, due to the limitations of conventional regulators. This means that supply voltage is held unnecessarily at its peak while clock frequency is reduced. Therefore, the resulting average supply voltage, and associated average power dissipation, is higher than the theoretical average required by the workload.
FIG. 1 illustrates a conventional multi-phase step-down switching regulator. One significant problem associated with using conventional single- and multi-phase regulators to achieve high slew rates is that such regulators exhibit asymmetric slew rates that can adversely impact system performance. Furthermore, at high switching frequencies, such circuits may require impractically small inductor values or an impractically high number of phases.
FIG. 2 illustrates the configuration of a multi-phase step-down switching regulator during positive slew. For input voltage VIN and output voltage VOUT, a conventional n-phase step-down switching regulator will command a maximum positive output current slew-rate by activating switches to short the switch node(s) SW1 and SW2 through SWN to VIN. This results in the sum of the inductor(s) current(s) to slew at the rate:(VIN−VREF)/L/n
FIG. 3 illustrates the configuration of a conventional multi-phase step-down switching regulator during negative slew. To command a maximum negative current slew rate, the controller 302 activates the switches to short the switch node(s) SW1 and SW2 through SWN to ground. This results in the sum of the inductor(s) current(s) to slew at the rate:(−VREF)/L/n
The positive output current slew rate is therefore a factor of (VIN−VREF)/(VREF) higher than the negative output current slew rate. For example, if VIN is at 12V and VOUT at 1V (low duty cycle case) regardless of the number of phases used, a traditional step-down switching converter features a maximum positive output current slew rate (SRP) that is 11 times faster than its maximum negative output current slew-rate (SRN).(SRP)/(SRN)=((VIN−VREF)/L/n)/((−VREF)/L/n)=(12−1)/1=11
In some applications, the positive voltage overshoot due to an off-loading event, where load current decreases, should be equal to the negative undershoot due to an equivalent loading event, where load current increases, in order for the output voltage not to drift away when the load current is stepping back and forth. As the result, a system may be limited by the off-loading output voltage overshoot due to the slow negative current slew rate of the inductor(s) and never takes advantage of the fast positive current slew-rate of the inductor(s). FIG. 4 illustrates this for a single-phase traditional buck converter going through a loading and off-loading event.
FIG. 5 shows an example of a single-phase regulator responding to a negative and then positive VREF voltage step. Due to the slow negative slew-rate, the output voltage takes a long time to slew down. Thus, the slow negative slew rate of the inductor current is again limiting how fast the output voltage can slew. As mentioned above, FIG. 5 illustrates an asymmetry that may be undesirable in some applications.